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Stacey Campbell
Woodland Hills, Los Angeles, California
staceycampbell@yahoo.com
FPGA digital design in Verilog and SystemVerilog, complex high-bandwidth fixed point filters, timing closure,
simulation and validation
Johnson & Johnson MedTech (formerly Auris Health), Westlake Village, California
— March 2020–April 2023
Principal Engineer, Digital Design
- Stereo rectification integrated with bi-cubic upscaling for 4K stereo monitor display.
- Xilinx GTH, SelectIO, and NI-DRU
8b10b input/output at various frequencies.
- Hybrid SPI and I2C implementations for non-compliant peripherals.
- Xilinx Video Processing Subsystem to implement 12G SDI.
- Ported substantial Intel/Altera ArriaV based project to a Xilinx UltraScale+ platform.
Red Digital Cinema, Thousand Oaks, California
— November 2014–March 2020
Senior Principal, Digital Design
Panavision, Woodland Hills, California
— January 2011–October 2014
Senior Engineer — Digital Design
- Design and implementation of 8K (7680x3240) 60fps CMOS sensor correction logic and image processing pipeline.
AltaSens, Westlake Village, California
— January 2008–January 2011
Senior Scientist
- HD video processing pipeline development.
- Sensor yield analysis.
- Automated randomized RTL and gate-level ASIC verification.
Micron Technology, Pasadena, California
— August 2006–December 2007
Team Lead — CMOS Imager Applications Engineering
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Managed CMOS Imager Applications Engineering team.
ESS Technology
(formerly Sierra Imaging,
Conexant Systems,
then Pictos Technologies),
Scotts Valley, California; Melbourne, Australia
— August 1996–August 2006
SoC and Image Processing ASIC Development
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Established ASIC development simulation test environment integrated with firmware development environment.
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Image processing ASIC verification for Raptor, Raptor II, and Raptor III products.
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Authored table driven assembler for custom DSP and processing blocks within each ASIC.
Digital Still Camera Firmware Development
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Designed, implemented and documented digital camera control firmware.
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Hardware drivers for lens stepper motors; non-volatile
memory devices; NTSC, PAL and LCD display devices; CDS chips; etc.
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Designed and implemented high-speed autofocus algorithm.
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Ported open source MP3 codec to embedded environment.
Anyware Fast, San Jose, California
— May 1995–August 1996
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SCO compatible X Server drivers and configuration files for PCI
graphics adapters using Cirrus GD5436 and GD5446 video chips.
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Ported 3D video game from 3DO to Sony Playstation (MIPS R3000) using
Sony's Playstation 1 development platform.
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Ported Sun's XIL imaging library for C++ and C to HP/UX.
Sun Microsystems, Mountain View,
California — February 1994–April 1995
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Coordinated Intel x86 issues for XGL (SunSoft's 3D graphics library).
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Integrated and qualified third-party developed 3D graphics drivers
for XGL.
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Compiled performance and quality numbers for XGL on x86 platforms.
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Device driver work for the Sun CG6 3D graphics adapter.
The Santa Cruz Operation, Santa Cruz, California
— July 1989–February
1994
HCR (Human Computing Resources), Toronto, Canada
— November 1987–May 1989
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Ported Oracle's V5.1 RDBMS, V6.0 RDBMS and associated utilities from 32 bit Unix environment
to Control Data Corporation Cyber 180 supercomputers.
Skills
Languages: Verilog, SystemVerilog, C, bash scripting
Tools: Vivado, Vitis, Vivado Debug (formerly Chipscope), git, Emacs Verilog-mode, Quartus, Signal Tap, Lattice Diamond, Lattice Reveal
Operating Systems: Fedora, Ubuntu, CentOS, Microsoft WSL
Other: Xilinx Ultrascale+, Ultrascale, Kintex-7, AXI4, SMPTE ST 2082, Altera/Intel Arria V
Education
BSc (Hons) Computer Science, La Trobe University, Melbourne, Australia, 1988.
Citizenship
Australia, United States
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